The article entitled “Low-Power Low-Voltage VLSI Operational Amplifier Cells” by Johan H. Huijsing et al., published in IEEE Transactions on Circuits and Systems, Vol. 42, No. 11, November 1995, describes voltage-efficient input stages (section II). The following considerations are made. A P-channel differential CMOS input stage has a common mode input voltage range that extends from a negative rail voltage up to a positive rail voltage minus a gate-source voltage VGS and a saturation voltage VDsat of a tail-current source. A N-channel differential CMOS input stage has a common mode input voltage range that extends from the positive rail voltage down the negative rail voltage plus the gate-source voltage VGS and the saturation voltage VDsat of a tail-current source. In case a so-called rail-to-rail input range is required, the aforementioned differential input stages, which are complementary, should be combined and at least one of the stages should function. FIG. 2 of the article illustrates such a topology. A summing circuit adds respective output currents of the differentials input stages. The summing circuit comprises four transistors M5-M8 that function as two folded current followers, while a pair M6, M8, simultaneously functions as a current mirror.